工作职责：

1.Analog mixed-signal design verification lead.
2.Responsible for and perform chip level and sub-system level analog mixed signal design verification.
3.Drive analog mixed-signal design verification plan, methodology and best practice and guideline towards first silicon success.
4.Create and verify System Verilog (or equivalent) models, test benches, and automated verification simulations for mixed signal circuit blocks.
5.Work closely with system, analog, and digital team to understand and verify system and sub-system functions and specifications.
6.Communicate and follow through with design team to resolve issues found during verification.
7.Provide specification, design review and test requirements documentation to guide support team (system, application, ATE test engineers etc.) to meet design quality, yield and schedule targets.
8.Characterize, and de-bug designs in the lab and test platform for mass production as necessary.
9.Must be a team player and self-starter.
1.模拟混合信号设计验证主管。
2.负责并执行芯片级和子系统级模拟混合信号设计验证。
3.推动模拟混合信号设计验证计划、方法、最佳实践和指南，以实现芯片首发成功。
4.创建和验证系统 Verilog（或等效）模型、测试平台以及混合信号电路块的自动验证仿真。
5.与系统、模拟和数字团队密切合作，了解和验证系统和子系统的功能和规格。
6.与设计团队沟通并跟进，解决验证过程中发现的问题。
7.提供规格、设计审查和测试要求文档，以指导支持团队（系统、应用、ATE 测试工程师等）满足设计质量、良率和进度目标。
8.根据需要在实验室和测试平台中对设计进行表征和调试，以进行大规模生产。
9.必须具有团队合作精神和自我启动能力。

任职资格：

1.MS degree in Electrical Engineering with 10+ or PhD degree with 8+ years of IC design verification or related experience.
2.Expert level experience and technical leadership in mixed signal design verification, UVM based DV, block level model specifications, simulation, system verilog real number modeling, writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups.
3.Extensive experience with system and modeling languages (MATLAB, RTL, SystemVerilog, SystemC, Verilog-AMS with wreal and poweraware).
4.Experience in modeling analog mixed-signal blocks such as bandgap, oscillator, bias network, amplifier, filters, analog/digital PLLs, ADC, DAC, LDO, and Class D AMP.
5.Expert level knowledge using common EDA tools and design verification methodology, such as Virtuoso, Incisive, Xcelium, Spectre, and SpectreX.
6.Extensive experience in creating test plan, scenarios and benches for mixed signal systems.
7.Ability to characterize and troubleshoot IC designs in the lab and ATE test floor.
8.Persevere to leave no stone unturned to make sure unexpected observations are root caused.
9.Outstanding communication and leadership skills.
10.Proficiency with digital design verification (including UVM) is a plus.
11.Class-D amplifier, PMIC, PLL and high performance sensor design verification background is a plus.
1.电气工程硕士10年以上或博士学位8年以上IC设计验证或相关经验。
2.在混合信号设计验证、基于UVM的DV、块级模型规范、仿真、系统verilog实数建模、编写检查器和断言、定制约束、使用覆盖组获取功能覆盖范围方面具有专家级经验和技术领导力。
3.丰富的系统和建模语言经验（MATLAB、RTL、SystemVerilog、SystemC、Verilog-AMS with wreal 和 poweraware）。
4.具有模拟混合信号模块建模经验，例如带隙基准、振荡器、偏置网络、放大器、滤波器、模拟/数字 PLL、ADC、DAC、LDO 和 D 类 AMP。
5.使用常见 EDA 工具和设计验证方法的专家级知识，例如 Virtuoso、Incisive、Xcelium、Spectre 和 SpectreX。
6.在创建混合信号系统测试计划、场景和平台方面拥有丰富的经验。
7.能够在实验室和 ATE 测试台中对 IC 设计进行表征和故障排除。
8.坚持不遗余力地确保意外观察的根源。
9.优秀的沟通和领导能力。
10.熟练掌握数字设计验证（包括UVM）者优先。
11.有D类功放、PMIC、PLL和高性能传感器设计验证背景者优先。