工作职责：

• Analog power stage sub-system and circuits block design, integration and simulation.
• Apply high-voltage and power analog design and layout best practice and guideline towards first silicon success.
• Work closely with system and analog lead to implement sub-system or blocks specifications.
• Work with digital team to ensure block mixed-signal functions are implemented and verified.
• Implement high-voltage power stage and power stage driver circuits in advanced BCD (Bipolar, CMOS, DMOS) processes.
• Provide specification, design review and test requirements documentation to guide support team (system, application, ATE test engineers etc.) to meet design quality, yield and schedule targets.
• Build behavioral modeling of analog and digital circuits with Matlab, Verilog A and System Verilog.
• Perform mixed signal simulations for verification of chip level and system level performance.
• Define layout requirements for layout engineers or complete the circuit layout autonomously.
• Characterize, and de-bug designs in the lab and test platform for mass production as necessary.
• Must be a team player and self-starter.

任职资格：

• MS degree in Electrical Engineering with 8+ or PhD degree with 5+ years of IC design experience.
• Silicon proven experience in CMOS or BCD analog mixed-signal design and layout.
• Silicon proven experience designing power related circuits such as switch-mode power supplies, battery chargers, LDOs, class-D amplifier and motor drivers.
• Strong knowledge of BCD silicon process technologies involving high voltage and high power design.
• Strong knowledge of transistor-level analog circuit simulation tools and with extensive experience with Cadence Virtuoso.
• Ability create and execute sub-system and block level AMS based verification test plans.
• Ability to characterize and troubleshoot IC designs in the lab and ATE test floor.
• Outstanding communication and leadership skills.
• Class-D amplifier, PMIC and automotive product design background is a plus.